1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device and more particularly to a manufacturing method suitable for forming a buried layer in a bipolar npn and pnp transistor mixed type semiconductor device.
2. Description of the Prior Art
FIGS. 5A-5F are cross-sectional views showing a conventional method for manufacturing an npn and pnp transistor mixed type semiconductor device. Referring to FIGS. 5A-5F, the conventional manufacturing method is described hereinafter.
First, as shown in FIG. 5A, into the surface of a p.sup.- type silicon substrate 1 are injected n-type impurities 2 such as antimony (Sb.sup.+) and arsenic (As.sup.+) at high concentration. The surface of the silicon substrate is oxidized at the same time that the n-type impurities 2 are thermally diffused, thereby an n.sup.+ type diffusion layer 3 and a thick oxide film 4 being formed as shown in FIG. 5B.
Next, as shown in FIG. 5C, the oxide film 4 is selectively etched away to form an opening 5. Masked with the oxide film 4, p-type impurities 6 such as boron (B.sup.+) are selectively injected into the n.sup.+ type diffusion layer 3. After a p-type diffusion layer 7 is formed by the thermal diffusion of the p-type impurities 6 as shown in FIG. 5D, the oxide film 4 is removed.
As shown in FIG. 5E, an n.sup.- type epitaxial layer 8 is grown epitaxially on the n.sup.+ type diffusion layer 3. At this time, the p-type impurities in the p-type diffusion layer 7 float up into the n.sup.- type epitaxial layer 8, so that a p-type buried diffusion layer 7a is formed in the interface of the n.sup.+ type diffusion layer 3 and the n.sup.- type epitaxial layer 8.
Subsequently, as shown in FIG. 5F, formed are element insulating films 9 which reach the p.sup.- type silicon substrate 1 from the top surface and p-type channel cut regions 10 on the undersurface thereof, thereby first and second element regions A and B being formed. In the n.sup.- type epitaxial layer 8 of the first element region A, a p.sup.- type collector diffusion layer 11, a p.sup.+ type collector extraction layer 12, an n-type base diffusion layer 13 and a p.sup.+ type emitter diffusion layer 14 are formed, so that a pnp transistor is formed. In the n.sup.- type epitaxial layer 8 of the second element region B, an n.sup.+ type collector extraction layer 15, a p-type base diffusion layer 16 and an n.sup.+ type emitter diffusion layer 17 are formed, so that an npn transistor is formed. Metal wirings 18 are mounted on the transistors, and thus the semiconductor device is accomplished.
A semiconductor device having the same structure as FIG. 5F is disclosed in IEDM84, pp. 753-756, "NEW SELF-ALIGNED COMPLEMENTARY BIPOLAR TRANSISTORS USING SELECTIVE-OXIDATION MASK" by H. Sadamatsu et al.
The conventional semiconductor device formed through the above-mentioned processes has been disadvantageous in that the thickness of the p-type buried diffusion layer 7a cannot be increased sufficiently.
Generally the n.sup.+ type diffusion layer 3 needs the impurity concentration of about 10.sup.20 cm.sup.-3. In order to form the p-type diffusion layer 7 on the surface of the n.sup.+ type diffusion layer 3 having such high concentration, it is necessary to inject the p-type impurities 6 having the concentration higher than the n.sup.+ type diffusion layer 3. In particular, for increasing the thickness of the p-type diffusion layer 7, the p-type impurities 6 having the concentration of much more than 10.sup.20 cm.sup.-3 must be injected. However, if such a large amount of p-type impurities 6 are injected, the crystallinity in the injected region cannot be retrieved. Hence, such injection is practically impossible. For this reason, the p-type diffusion layer 7 to be formed is quite thin, and accordingly the p-type buried diffusion layer 7a formed by the impurities in the p-type diffusion layer 7 which float up into the n.sup.- type epitaxial layer 8 grows at most about 0.3 .mu.m in thickness. As a result, the resistance of the p-type buried diffusion layer 7a becomes high, and the collector resistance of the pnp transistor cannot be reduced sufficiently.